Short Course 2: FPGA Programming on the USRP with the RFNoC Framework

The RFNoC (RF Network-on-Chip) software framework from Ettus Research is meant to decrease the development time for experienced FPGA engineers seeking to integrate IP into the USRP signal processing chain. RFNoC is the architecture for USRP devices that use Xilinx 7-series FPGAs (E310, E312, E320, X300, X310, N310, N320). RFNoC is built around a packetized network infrastructure in the FPGA that handles the transport of control and sample data between the host CPU and the radio. Users target their custom algorithms to the FPGA in the form of Computation Engines (CE), which are processing blocks that attach to this network. CEs act as independent nodes on the network that can receive and transmit data to any other node (e.g., another CE, the radio block, or the host CPU). Users can create modular, FPGA-accelerated SDR applications by chaining CEs into a flow graph. RFNoC is supported in UHD and GNU Radio. In this workshop, we will present an interactive hands-on tutorial on RFNoC, including a discussion on its design and capabilities, demonstrations of several existing examples, and a walk-through on implementing a user-defined CE and integrating the CE into both UHD and GNU Radio.

Prerequisites: Attendees should have some previous experience with Linux and using the Linux command line, and basic familiarity with a programming language such as C, C++, or Python, and have basic understanding of fundamental concepts in DSP and RF. Attendees should also have some basic familiarity with Verilog. Extensive or deep experience with these topics is not necessary. Attendees do not have to bring any USRP radios or laptop computers. All necessary hardware and software will be provided in the workshop. Attendees may optionally bring their own laptops and/or radios for use in the workshop. Please contact “support@ettus.com” for specific setup and configuration requirements.

Presenters: Jonathon Pendlum is a software engineer with over ten years of experience in Software Defined Radio, FPGA development, and embedded systems. He is a Northeastern University alumni and received a M.S. in Computer Engineering in 2014. After graduating, he joined Ettus Research and led the FPGA development of RF Network-on-Chip (RFNoC). He is currently a self-employed contractor focusing on projects related to Software Defined Radio and FPGA design.

Neel Pandeya is a senior software engineer and manager of the Technical Support Group at Ettus Research, a National Instruments Company, in Santa Clara, California, USA. His background and interests are in open-source software development, kernel and embedded software development, wireless and cellular communications, DSP and signal processing, and software-defined radio (SDR). Prior to joining Ettus Research in 2014, he worked at several start-up and mid-sized companies, such as Envoy Networks, Range Networks, Draper Laboratory, Texas Instruments, and Teradyne. He is a co-founder and co-organizer of the New England Workshop for SDR (NEWSDR), and is a co-organizer of the GNU Radio Conference. He holds a Bachelor’s Degree in electrical engineering (BSEE) from Worcester Polytechnic Institute (WPI), and a Master’s Degree in electrical engineering (MSEE) from Northeastern University. He has an Amateur Radio License, and is aspiring to obtain a private pilot license.

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