Ettus Research’s RFNoC (RF Network-on-Chip) software is meant to decrease the development time for experienced FPGA engineers seeking to integrate IP into the USRP signal processing chain. RFNoC is the architecture for USRP devices that use Xilinx 7-series FPGAs (E310, E312, X300, X310). RFNoC is built around a packetized network infrastructure in the FPGA that handles the transport of control and sample data between the host CPU and the radio. Users target their custom algorithms to the FPGA in the form of Computation Engines (CE), which are processing blocks that attach to this network. CEs act as independent nodes on the network that can receive and transmit data to any other node (e.g., another CE, the radio block, or the host CPU). Users can create modular, FPGA-accelerated SDR applications by chaining CEs into a flow graph. RFNoC is supported in UHD and GNU Radio. In this workshop, we will present an interactive hands-on tutorial on RFNoC, including a discussion on its design and capabilities, demonstrations of several existing examples, and a walk-through on implementing a user-defined CE and integrating the CE into GNU Radio.
Attendees should have some previous experience with Linux and using the Linux command line, and basic familiarity with a programming language such as C, C++, or Python, and have basic understanding of fundamental concepts in DSP and RF. Attendees should also have some basic familiarity with Verilog. Extensive or deep experience with
these topics is not necessary.
Attendees do not have to bring any USRP radios or laptop computers. All necessary hardware and software will be provided in the workshop.
Attendees may optionally bring their own laptops for use in the workshop. The laptop should have a minimum of 4 GB memory, 60 GB of free disk space, one Ethernet port available, and one USB 3.0 port available. Attendees are expected to install VirtualBox 5.1.26 onto the laptop. The laptop may run Windows, Mac, or Linux.