Hands-On SDR Experimentation: Hands-On Tutorial on FPGA Computing for SDR with RFNoC

Ettus Research has introduced a platform called RF Network-on-Chip (RFNoC) which makes FPGA computing for SDR more accessible and flexible. RFNoC is a new architecture for USRP devices that use Xilinx 7-series FPGAs (E310, X300, and X310).  RFNoC is built around a packetized network infrastructure in the FPGA that handles the transport of control and sample data between the host CPU and the radio. Users target their custom algorithms to the FPGA in the form of Computation Engines (CE), which are processing blocks that attach to this network. CEs act as independent nodes on the network that can receive and transmit data to any other node (e.g., another CE, the radio block, or the host CPU). This architecture permits scalable designs that can distribute processing across many nodes. Users can create modular, FPGA-accelerated SDR applications by chaining CEs into a flow graph. RFNoC is supported in UHD and GNU Radio. In this workshop, we will present an interactive tutorial on RFNoC, including a discussion on its design and capabilities, demonstrations of several existing examples, and a walk-through on implementing a user-defined CE and integrating the CE into GNU Radio.

Prerequisites:

  • Attendees must create Xilinx user accounts at least three days before the workshop, in order to obtain Xilinx licenses for the free WebPack Edition of Vivado version 2015.4.
  • Attendees are expected to bring their own laptops to the workshop. The laptop should have at least 2 GB memory, have at least one Ethernet port and one USB 3.0 port, and be able to boot into a Linux environment from a USB 3.0 flash drive.

USB flash drives and USRP hardware will be provided in the workshop.

Enrollment is limited to 20 people.

Facilitators

Jonathon Pendlum

Wan Liu

Neel Pandeya